AD8380 Просмотр технического описания (PDF) - Analog Devices
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AD8380 Datasheet PDF : 16 Pages
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AD8380
SVGA System Operation
An SVGA system is characterized by the requirement of six
channels of panel drive for each displayed color. Such a system
would use a single AD8380 per color.
With E/O and all address bits A[0:2] set high, channel loading
commences on the first rising edge of CLK following a valid
assertion of the Start Sequence (STSQ) input. The second stage
latches, and therefore the video outputs, are updated on the
first falling edge of the clock following a valid Transfer (XFR)
signal. (See Figure 5 for signal timing details.)
DB[0:9]
CLK
STSQ/CS
5
t3
t4
0
t7
2.0V
0.8V
5
t1
t2
0
t7
2.0V
0.8V
XFR
t5
t6
Figure 5. Sequenced SVGA Timing (A[0:2] = HIGH, E/O =
HIGH, See Table I)
Table I. Sequenced SVGA Data Byte to Channel Assignment
Channel Number
E/O = HIGH
R/L = LOW
VID0
VID1
VID2
VID3
VID4
VID5
Data Byte Number
0
1
2
3
4
5
Load Sequence Switching (Right/Left Control)
To facilitate image mirroring, the order in which channels are
loaded can be easily switched. When the voltage on the right/left
control input (R/L) is low, the internal sequencer will load data
starting with Channel 0 and counting up to Channel 5. When
this voltage is high, channel loading will be in reverse order, from
Channel 5 down to Channel 0.
XGA System Operation
In an XGA system, twelve column drivers (two AD8380s) are
required for each color (refer to Figure 6). An “even/odd”
system, in which one AD8380 drives even numbered columns
and another drives odd numbered columns, can be easily imple-
mented as detailed in Figures 7 and 8. A clock at one-half the
pixel rate is applied to the CLK input. Even bytes are loaded on
the rising edge of the clock, while odd bytes are loaded on the
falling edge. Identifying whether a chip is to load on rising or falling
edges is done by setting the proper level on the E/O input.
1 COLOR OF ‘EVEN/ODD’ XGA
DVCC
STSQ_A
STSQ_B
XFR
PANEL
E/O_A
CONTROLLER R/L
CLKIN
INV
E/O_B
STSQ/CS
3
A[0:2]
XFR
AD8380
DEVICE “A”
E/O
R/L
VIDEO 6
OUT
INV
CLK
DB[0:9]
IMAGE
PROCESSOR
VIDEO
DB[0:9]
10
DCLK/2
DVCC
STSQ/CS
3
A[0:2]
XFR AD8380
E/O DEVICE “B”
R/L
VIDEO 6
INV
OUT
CLK
DB[0:9]
Figure 6. Even/Odd: Outputs of Devices A and B are
Configured as Even and Odd Data Channels and Loading
Sequence Is Defined by Status of E /O and R /L Inputs
DB[0:9] 0
10
11
0
CLK
(EVEN
CHIP)
STSQ/CS
(EVEN
CHIP)
CLK
(ODD
CHIP)
STSQ/CS
(ODD
CHIP)
t3 t4
t3 t4
9
10
11
t1
t2
t1
t2
t5
t6
XFR
A0:A2 = HIGH
Figure 7. Sequenced Even/Odd XGA Timing, A[0:2] =
HIGH (See Table II)
Table II. Sequenced Even/Odd XGA Data Byte to
Channel Assignment
Channel Number
E/O = HIGH
VID0
VID1
VID2
VID3
VID4
VID5
E/O = LOW
VID0
VID1
VID2
VID3
VID4
VID5
Data Byte Number
R/L = LOW
R/L = HIGH
0
10
2
8
4
6
6
4
8
2
10
0
1
11
3
9
5
7
7
5
9
3
11
1
–10–
REV. B
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