AD7980ARMZRL7 Просмотр технического описания (PDF) - Analog Devices
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AD7980ARMZRL7 Datasheet PDF : 26 Pages
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AD7980
Data Sheet
−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 3.3 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 5.
Parameter
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min
500
290
1.2
10
22
23
6
6
3
5
10
0
5
5
2
3
Typ Max Unit
833 kSPS
800 ns
ns
μs
ns
ns
ns
ns
ns
ns
14
21
ns
18
40
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
22
ns
Timing Diagrams
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
tDELAY
VIH2
VIL2
Y% VIO1
tDELAY
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. F | Page 6 of 26
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