AD7787 Просмотр технического описания (PDF) - Analog Devices
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AD7787 Datasheet PDF : 20 Pages
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Table 7. Channel Selection
CH1
CH0
0
0
0
1
1
0
1
1
Channel
AIN1(+) − AIN1(−)
AIN2
AIN1(−) − AIN1(−)
VDD Monitor
AD7787
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0×8C)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bits RS1 and RS0 with 0s. Table 8 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in the parenthesis indicates the power-on/reset default status of that bit.
SR7
RDY (1)
SR6
ERR (0)
SR5
SR4
SR3
SR2
0 (0)
0 (0)
1 (1)
1 (1)
SR1
CH1 (0)
SR0
CH0 (0)
Table 8. Status Register Bit Designations
Bit
Bit
Location Name Description
SR7
RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the
ADC data register has been read or a period of time before the data register is updated with a new conversion result
to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode.
The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status
register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC
data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write
operation to start a conversion.
SR5 to
0
SR4
These bits are automatically cleared.
SR3 to
1
SR2
These bits are automatically set.
SR1 to
SR0
CH1 to These bits indicate which channel is being converted by the ADC.
CH0
Rev. 0 | Page 11 of 20
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