AD7747(RevPrC) Просмотр технического описания (PDF) - Analog Devices
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AD7747 Datasheet PDF : 20 Pages
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AD7747
Preliminary Technical Data
Parameter
Min
Typ
Average VIN Input Current
300
Analog VIN Input Current Drift
±50
Power Supply Rejection
80
Power Supply Rejection
90
Normal Mode Rejection
75
50
Common-Mode Rejection
95
INTERNAL VOLTAGE REFERENCE
Voltage
1.169
1.17
Drift vs. Temperature
5
EXTERNAL VOLTAGE REFERENCE INPUT
Differential REFIN Voltage2
0.1
2.5
Absolute REFIN Voltage2
GND − 0.03
Average REFIN Input Current
400
Average REFIN Input Current Drift
±50
Common-Mode Rejection
80
SERIAL INTERFACE LOGIC INPUTS
(SCL, SDA)
VIH Input High Voltage
VIL Input Low Voltage
Hysteresis
2.1
150
Input Leakage Current (SCL)
±0.1
OPEN-DRAIN OUTPUT (SDA)
VOL Output Low Voltage
IOH Output High Leakage Current
0.1
LOGIC OUTPUT (RDY)
VOL Output Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
VOH Output High Voltage
4.0
VDD – 0.6
POWER REQUIREMENTS
VDD-to-GND Voltage
4.75
2.7
IDD Current
1
TBD
TBD
IDD Current Power-Down Mode
Max
Unit
nA/V
pA/V/°C
dB
dB
dB
dB
dB
1.171
V
ppm/°C
VDD
VDD + 0.03
V
V
nA/V
pA/V/°C
dB
V
0.8
V
mV
±1
µA
0.4
V
1
µA
0.4
V
V
0.4
V
V
5.25
V
3.6
V
TBD
mA
mA
mA
TBD
µA
Test Conditions/Comments
Internal reference, VIN = VREF/2
External reference, VIN = VREF/2
50 Hz ± 1%, conversion time = 122.1 ms
60 Hz ± 1%, conversion time = 122.1 ms
VIN = 1 V
TA = 25°C
ISINK = −6.0 mA
VOUT = VDD
ISINK = 1.6 mA, VDD = 5 V
ISOURCE = 200 µA, VDD = 5 V
ISINK = 100 µA, VDD = 3 V
ISOURCE = 100 µA, VDD = 3 V
VDD = 5 V, nominal
VDD = 3.3 V, nominal
Digital inputs equal to VDD or GND
VDD = 5 V
VDD = 3.3 V
Digital inputs equal to VDD or GND
1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At
different temperatures, compensation for gain drift over temperature is required.
4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger
offset can be removed using CAPDACs.
5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
6 The CAPDAC resolution is six bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further
reduce the CIN offset or the unchanging CIN component.
7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.
8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure TBD, with total serial resistance <100 Ω.
9 Full-scale error applies to both positive and negative full scale.
Rev. PrC | Page 4 of 20
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