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AD7703

LC2MOS 20-Bit A/D Converter

Analog Devices 

AD7703

GENERAL DESCRIPTION

The AD7703 is a 20-bit A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low frequency signals such as those representing chemical,

physical, or biological processes. It contains a charge-balancing

(⌺-⌬) ADC, calibration microcontroller with on-chip static

RAM, clock oscillator, and serial communications port.

The analog input signal to the AD7703 is continuously sampled

at a rate determined by the frequency of the master clock, CLKIN.

A charge-balancing A/D converter (⌺-⌬ modulator) converts

the sampled signal into a digital pulse train whose duty cycle

contains the digital information. A six-pole Gaussian digital

low-pass filter processes the output of the ⌺-⌬ modulator and

updates the 20-bit output register at a 4 kHz rate. The output

data can be read from the serial port randomly or periodically at

any rate up to 4 kHz.

+5V

ANALOG

SUPPLY

10␮F

0.1␮F

AVDD

DVDD

SLEEP

MODE

RANGE

SELECT

VOLTAGE

REFERENCE

2.5V

DRDY

VREF

AD7703 CS

BP/UP

SCLK

SDATA

CALIBRATE

CAL

CLKIN

ANALOG

INPUT

ANALOG

GROUND

0.1␮F

–5V

ANALOG

SUPPLY 10␮F

AIN

AGND

AVSS

CLKOUT

SC1

SC2

DGND

DVSS

0.1␮F

DATA READY

READ

(TRANSMIT)

SERIAL CLOCK

SERIAL DATA

0.1␮F

Figure 7. Typical System Connection Diagram

The AD7703 can perform self-calibration using the on-chip

calibration microcontroller and SRAM to store calibration

parameters. A calibration cycle may be initiated at any time

using the CAL control input.

Other system components may also be included in the calibra-

tion loop to remove offset and gain errors in the input channel.

For battery operation, the AD7703 also offers a standby mode

that reduces idle power consumption to typically 10 µW.

THEORY OF OPERATION

The general block diagram of a ⌺-⌬ ADC is shown in Figure 8.

It contains the following elements:

1. A sample-hold amplifier

2. A differential amplifier or subtracter

3. An analog low-pass filter

4. A 1-bit A/D converter (comparator)

5. A 1-bit DAC

6. A digital low-pass filter

S/H AMP

ANALOG

LOW-PASS

FILTER

COMPARATOR

DIGITAL

FILTER

DAC

DIGITAL DATA

Figure 8. General ⌺-⌬ ADC

In operation, the analog signal sample is fed to the subtracter,

along with the output of the 1-bit DAC. The filtered difference

signal is fed to the comparator, whose output samples the differ-

ence signal at a frequency many times that of the analog signal

sampling frequency (oversampling).

Oversampling is fundamental to the operation of ⌺-⌬ ADCs.

Using the quantization noise formula for an ADC

SNR = (6.02 ¥ number of bits + 1.76) dB

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

The AD7703 samples the input signal at 16 kHz, which spreads

the quantization noise from 0 kHz to 8 kHz. Since the specified

analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the

noise energy in this bandwidth would be only 1/800 of the total

quantization noise, even if the noise energy were spread evenly

throughout the spectrum. It is reduced still further by analog

filtering in the modulator loop, which shapes the quantization

noise spectrum to move most of the noise energy to frequencies

above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range

is conditioned to the 20-bit level in this fashion.

The output of the comparator provides the digital input for the

1-bit DAC, so the system functions as a negative feedback loop

that minimizes the difference signal. The digital data that repre-

sents the analog input voltage is in the duty cycle of the pulse train

appearing at the output of the comparator. It can be retrieved as

a parallel binary data-word using a digital filter.

⌺-⌬ ADCs are generally described by the order of the analog

low-pass filter. A simple example of a first-order, ⌺-⌬ ADC is

shown in Figure 8. This contains only a first-order, low-pass

filter or integrator. It also illustrates the derivation of the alter-

native name for these devices: charge-balancing ADCs.

The AD7703 uses a second-order, ⌺-⌬ modulator and a sophis-

ticated digital filter that provides a rolling average of the sampled

output. After power-up or if there is a step change in the input

voltage, there is a settling time that must elapse before valid

data is obtained.

REV. E

–7–

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