AD73360L Просмотр технического описания (PDF) - Analog Devices
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AD73360L Datasheet PDF : 33 Pages
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AD73360L
Parameter
AD73360LA
Min
Typ Max
Unit
Test Conditions/Comments
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD – 0.4
0
–10
VDD
V
0.4
V
+10 µA
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
IDD8
2.7
3.6
V
2.7
3.6
V
See Table I
NOTES
1Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Conditions
Total
Current
(Max) SE
MCLK
ON
Comments
ADCs Only On
25
REFCAP Only On
1.0
REFCAP and REFOUT Only On 3.5
All Sections On
26.5
All Sections Off
1.0
All Sections Off
0.05
1
Yes
0
No
0
No
1
Yes
0
Yes
0
No
REFOUT Disabled
REFOUT Disabled
REFOUT Enabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
TIMING CHARACTERISTICS (AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless other-
wise noted.)
Parameter
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Limit at
TA = –40؇C to +85؇C
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
Description
See Figure 1.
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4.
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup before SCLK Low
SDI/SDIFS Hold after SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold after SCLK High
SDO Hold after SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
REV. 0
–3–
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