AD7143ACPZ-1500RL7 Просмотр технического описания (PDF) - Analog Devices
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AD7143ACPZ-1500RL7 Datasheet PDF : 56 Pages
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AD7143
SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
23
Resolution
CIN Input Range1
No Missing Codes
16
CIN Input Leakage
Total Unadjusted Error
Output Noise (Peak-to-Peak)
Output Noise (RMS)
Parasitic Capacitance
Typ Max Unit
25
26 ms
16
Bit
±2
pF
Bit
25
nA
±20 %
7
Codes
3
Codes
0.8
Codes
0.5
Codes
40 pF
CBULK Offset Range1
CBULK Offset Resolution
Low Power Mode Delay Accuracy
EXCITATION SOURCE
Frequency
Output Voltage
Short-Circuit Source Current
Short-Circuit Sink Current
Maximum Output Load
CSHIELD Output Drive
CSHIELD Bias Level
LOGIC INPUTS (SCLK, SDA)
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Voltage
IIL Input Low Voltage
Hysteresis
OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)
VOL Output Low Voltage
IOH Output High Leakage Current
POWER
VCC
VDRIVE
ICC
±20
pF
156.25
fF
5
%
237.5
240
20
50
250
10
VCC/2
262.5 kHz
VCC V
mA
mA
pF
μA
V
0.7 × VDRIVE
−1
150
V
0.4 V
μA
1
μA
mV
0.4 V
+0.1 ±1 μA
2.6
3.3
3.6 V
1.65
3.6 V
0.9
1
mA
20 μA
16
30 μA
4.5 μA
2.25 15 μA
1 CIN and CBULK are defined as follows:
PLASTIC OVERLAY
SENSOR BOARD
CAPACITIVE SENSOR
CIN
CBULK
Test Conditions/Comments
Eight conversion stages in sequencer, decimation = 256
Guaranteed by design, but not production tested
Decimation rate = 128
Decimation rate = 256
Decimation rate = 128
Decimation rate = 256
Parasitic capacitance to ground, per CIN input guaranteed
by characterization
% of 200 ms, 400 ms, 600 ms, or 800 ms
Capacitance load on source to ground
VIN = GND
ISINK = −1 mA
In full power mode
Low power mode, converter idle, TA = 25°C
Low power mode, converter idle
Full shutdown, TA = 25°C
Full shutdown
Rev. 0 | Page 3 of 56
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