AD677KR Просмотр технического описания (PDF) - Analog Devices
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AD677KR Datasheet PDF : 16 Pages
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AD677
PIN DESCRIPTION
DIP Pin SOIC Pin
1
1
Type
SAMPLE
Name
DI
2
2
CLK
DI
3
3
4
6, 7
5
8
8
12
.9
15
10
16
11
17
12
21
13
22, 23
14
26
15
27
SDATA
DO
DGND
P
VCC
P
AGND
P
AGND SENSE AI
VIN
AI
VREF
AI
VEE
P
VDD
P
SCLK
DO
BUSY
DO
16
28
CAL
DI
6, 7
4, 5, 9, 10, 11, NC
_
13, 14, 18, 19,
20, 24, 25
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
Description
VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE
controls the suite of the internal sample-hold amplifier and the falling edge
initiates conversion. During calibration, SAMPLE should be held LOW. If
HIGH during calibration, diagnostic information will appear on SDATA.
Master Clock Input. The AD677 requires 17 clock pulses to execute a
conversion. CLK is also used to derive SCLK.
Serial Output Data Controlled by SCLK.
Digital Ground.
+12 V Analog Supply Voltage.
Analog Ground.
Analog Ground Sense.
Analog Input Voltage.
External Voltage Reference Input.
–12 V Analog Supply Voltage.
+5 V Logic Supply Voltage.
Clock Output for Data Read, derived from CLK.
Status Line for Converter. Active HIGH, indicating a conversion or
calibration in progress.
Calibration Control Pin.
No Connection. No connections should be made to these pins.
SAMPLE 1
16 CAL
CLK 2
15 BUSY
SDATA 3
14 SCLK
DGND 4
VCC 5
NC 6
NC 7
AD677
TOP VIEW
(Not to Scale)
13 VDD
12 VEE
11 VREF
10 VIN
AGND
8
9
NC = NO CONNECT
DIP Pinout
AGND
SENSE
SAMPLE 1
28 CAL
CLK 2
27 BUSY
SDATA 3
26 SCLK
NC 4
25 NC
NC 5
24 NC
DGND1 6
DGND2 7
VCC 8
NC 9
AD677
TOP VIEW
(Not to Scale)
23 VDD1
22 VDD2
21 VEE
20 NC
NC 10
19 NC
NC 11
18 NC
AGND 12
17 VREF
NC 13
16 VIN
NC 14
15 AGND
SENSE
NC = NO CONNECT
SOIC Pinout
–6–
REV. A
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