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AD5666
(Rev.:RevA)

Quad, 16-Bit DAC with 5 ppm/°C On-Chip Reference in 14-Lead TSSOP

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LDAC 1

SYNC 2

VDD 3

VOUTA 4

VOUTC 5

POR 6

VREFIN/VREFOUT 7

AD5666

TOP VIEW

(Not to Scale)

14 SCLK

13 DIN

12 GND

11 VOUTB

10 VOUTD

9 CLR

8 SDO

Figure 5. 14-Lead TSSOP (RU-14)

AD5666

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in

on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising

edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

3

VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled

with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

4

VOUTA

5

VOUTC

6

POR

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up

the part to midscale.

7

VREFIN/VREFOUT

The AD5666 has a common pin for reference input and reference output. When using the internal

reference, this is the reference output pin. When using an external reference, this is the reference input

pin. The default for this pin is as a reference input.

8

SDO

Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading

back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge

of SCLK and is valid on the falling edge of the clock.

9

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

ignored. When CLR is activated, the input register and the DAC register are updated with the data

contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

10

VOUTD

11

VOUTB

12

GND

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

13

DIN

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input.

14

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates of up to 50 MHz.

Rev. A | Page 11 of 28

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