AD5024 Просмотр технического описания (PDF) - Analog Devices
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AD5024 Datasheet PDF : 28 Pages
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AD5024/AD5044/AD5064
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Limit at TMIN, TMAX;
VDD = 4.5 V to 5.5 V
20
10
10
16.5
5
5
0
1.9
10.5
17
20
20
10
10
10.6
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
μs min
ns min
ns min
ns min
ns min
ns min
μs min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time (all channel update)
SYNC rising edge to SCLK fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
1 Guaranteed by design and characterization; not production tested.
SCLK
SYNC
DIN
LDAC1
t8
t4
DB23
t6
t5
LDAC2
CLR
t12
VOUT
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3
t2
t9
t7
DB0
t13
t10
t11
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 28
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