AD1970 Просмотр технического описания (PDF) - Analog Devices
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AD1970 Datasheet PDF : 20 Pages
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AD1970
Pin No.
18
19
Pin Name
VIN_IAMPR
CAPLP
20
CAPLN
21
CAPRP
22
CAPRN
23
PVDD
24
PLL_LF
25
PGND
26
VID_IN
27
NC
28
PLL_MODE0
29
PLL_MODE1
30
MCLK
31
VID_PRES
32
XOUT
33
XIN
34
GPIO0
35
GPIO1
36
DGND
37
DVDD
38
GPIO2
39
GPIO3
40
SDATA
41
BCLK
42
LRCLK
43
DIG_IN_EN
44
SDA
45
SCL
46
ADR1
47
ADR0
48
DGND
Input/Output
IN
I/O
I/O
I/O
I/O
IN
IN
IN
IN
OUT
OUT
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN/OUT
IN
IN
IN
Description
Negative input of internal op amp for right channel input amplifier.
ADC Filter Capacitor Connection (positive left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
ADC Filter Capacitor Connection (negative left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
ADC Filter Capacitor Connection (positive right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
ADC Filter Capacitor Connection (negative right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
PLL Power. 3.3 V nominal. Bypass capacitors should be placed close to this pin and
connected directly to the PLL ground.
PLL Loop Filter Connection.
PLL Ground. Connect to DGND.
Composite Video Input. Composite video signal input to the sync separator. The sync
output is connected to a PLL that generates the clocks for the AD1970. This pin has an
input impedance of 2 kΩ.
No Connect.
PLL Mode Select Pin 0. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
PLL Mode Select Pin 1. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
Master Clock Input. This input is used to generate the internal master clock if it is not
derived from the composite video signal on VID_IN. The master clock frequency must be
either fs or 256 × fs, where fs is the input sampling frequency. The PLL_CTRLx pins should
be set to accept the appropriate MCLK input frequency.
Video Present Flag. A high logic level on this pin indicates that a valid composite video
signal is present on the VID_IN pin. Open-drain output.
Crystal Oscillator Output. This pin is the output of the on-board oscillator and should be
connected to one side of a crystal.
Crystal Oscillator Input. This pin is the input to the on-board oscillator and should be
connected to one side of a crystal.
General Purpose I/O 0. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
General Purpose I/O 1. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
Digital Ground.
Digital Power.
General Purpose I/O 2. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
General Purpose I/O 3. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
Serial Data Input/Output (Before BTSC Encoding). Digital input to the BTSC encoder or
output of the ADC. The serial format is selected by writing to Bits 3:2 of Control Register 1.
Bit Clock Input/Output. Serial bit clock for clocking in the serial data. The interpretation of
BCLK changes according to the serial mode, which is set by writing to the control
registers.
Left/Right Clock Input/Output. Left/right clock for framing the serial input data. The
interpretation of the LRCLK changes according to the serial mode, set by writing to the
control registers.
Digital Input Enable (active high).
I2C Serial Data Input/Output.
I2C Serial Clock Input.
I2C Address 1. The address of the I2C port is set by these pins according to Table 16.
I2C Address 0. The address of the I2C port is set by these pins according to Table 16.
Digital Ground.
Rev. 0 | Page 8 of 20
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