AD1928 Просмотр технического описания (PDF) - Analog Devices
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AD1928 Datasheet PDF : 32 Pages
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Parameter
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLSKEW
tDDS
tDDH
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALSKEW
tABDD
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
tDLH
AD1928
Condition
CCLK high
CCLK low
CCLK frequency
CIN setup
CIN hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
COUT tristate
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
Comments
See Figure 11, except where otherwise noted
fCCLK = 1/tCCP, only tCCP shown in Figure 11
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK falling
Not shown in Figure 11
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 11
From CCLK falling
See Figure 24
Slave mode
Slave mode
To DBCLK rising, slave mode
From DBCLK rising, slave mode
From DBCLK falling, master mode
To DBCLK rising
From DBCLK rising
See Figure 25
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
Min Max Unit
35
ns
35
ns
10 MHz
10
ns
10
ns
10
ns
10
ns
10
ns
30 ns
30 ns
30
ns
30 ns
10
ns
10
ns
10
ns
5
ns
−8 +8 ns
10
ns
5
ns
10
ns
10
ns
10
ns
5
ns
−8 +8 ns
18 ns
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
10
ns
5
ns
18 ns
10
ns
10
ns
10
ns
5
ns
Rev. 0 | Page 7 of 32
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