HM514400CLS-8 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM514400CLS-8

1,048,576-word × 4-bit Dynamic Random Access Memory

Hitachi -> Renesas Electronics 

HM514400B/BL, HM514400C/CL Series

Notes: 1. AC measurements assume tT = 5 ns.

2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the

maximum recommended value shown in this table, tRAC exceeds the value shown.

3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.

4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).

5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).

6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not

referred to output voltage levels.

7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH and VIL.

8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified

as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time

is controlled exclusively by tCAC.

9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified

as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time

is controlled exclusively by tAA.

10. tWCS, tRWD, tCWD, tCPW and tAWD are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write

cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;

if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tCPW ≥ tCPW (min) and tAWD ≥ tAWD (min), the cycle is a

read-modify-write and the data output will contain data read from the selected cell; if neither of

the above sets of conditions is satisfied, the condition of the data out (at access time) is

indeterminate.

11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading

edge in a delayed write or read-modify-write cycle.

12. tRASC defines RAS pulse width in fast page mode cycles.

13. Access time is determined by the longest among tAA, tCAC and tACP.

14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization

cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter

is used, a minimum of eight CAS-before-RAS refresh cycles is required.

15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data

to the device.

16. Test mode operation specified in this data sheet is 2-bit test function controlled by control

address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS

(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read

cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the

condition of the output data is high level. When the state of test bits do not accord, the condition

of the output data is low level. In order to end this test mode operation, perform a RAS-only

refresh cycle or a CAS-before-RAS refresh cycle.

17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2 ns to 5 ns

for the specified value. These parameters should be specified in test mode cycles by adding the

above value to the specified value in this data sheet.

18. Either tRCH or tRRH must be satisfied

19. tRAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle.

20. tCAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.

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