AD1877 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD1877

Single-Supply 16-Bit ΣΔ Stereo ADC

Analog Devices 

The ground planes should be tied together at one spot under-

neath the center of the package with an approximately 3 mm

trace. This ground plane technique also minimizes RF transmis-

sion and reception.

LRCK 1

WCLK 2

BCLK 3

DVDD1 4

DGND1 5

RDEDGE 6

S/M 7

384/256 8

AVDD 9

VINL 10

CAPL1 11

CAPL2 12

AGNDL 13

VREFL 14

DIGITAL GROUND PLANE

ANALOG GROUND PLANE

28 CLKIN

27 TAG

26 SOUT

25 DVDD2

24 DGND2

23 RESET

22 MSBDLY

21 RLJUST

20 AGND

19 VINR

18 CAPR1

17 CAPR2

16 AGNDR

15 VREFR

Figure 4. Recommended Ground Plane

Each reference pin (14 and 15) should be bypassed with a 0.1 µF

ceramic chip capacitor in parallel with a 4.7 µF tantalum capaci-

tor. The 0.1 µF chip cap should be placed as close to the pack-

age pin as possible, and the trace to it from the reference pin

should be as short and as wide as possible. Keep this trace away

from any analog traces (Pins 10, 11, 12, 17, 18, 19)! Coupling

between input and reference traces will cause even order har-

monic distortion. If the reference is needed somewhere else on

the printed circuit board, it should be shielded from any signal

dependent traces to prevent distortion.

Wherever possible, minimize the capacitive load on the digital

outputs of the part. This will reduce the digital spike currents

AD1877

drawn from the digital supply pins and help keep the IC sub-

strate quiet.

How to Extend SNR

A cost-effective method of improving the dynamic range and

SNR of an analog-to-digital conversion system is to use multiple

AD1877 channels in parallel with a common analog input. This

technique makes use of the fact that the noise in independent

modulator channels is uncorrelated. Thus every doubling of the

number of AD1877 channels used will improve system dynamic

range by 3 dB. The digital outputs from the corresponding deci-

mator channels have to be arithmetically averaged to obtain the

improved results in the correct data format. A microprocessor,

either general-purpose or DSP, can easily perform the averaging

operation.

Shown below in Figure 5 is a circuit for obtaining a 3 dB

improvement in dynamic range by using both channels of a

single AD1877 with a mono input. A stereo implementation

would require using two AD1877s and using the recommended

input structure shown in Figure 2. Note that a single microproces-

sor would likely be able to handle the averaging requirements

for both left and right channels.

SINGLE

CHANNEL

INPUT

AD1877

RECOMMENDED

INPUT BUFFER

VINR

AD1877

DIGITAL

AVERAGER

SINGLE

CHANNEL

OUTPUT

VINL

Figure 5. Increasing Dynamic Range By Using Two

AD1877 Channels

DIGITAL INTERFACE

Modes of Operation

The AD1877’s flexible serial output port produces data in

two’s-complement, MSB-first format. The input and output sig-

nals are TTL logic level compatible. Time multiplexed serial

data is output on SOUT (Pin 26), left channel then right chan-

nel, as determined by the left/right clock signal LRCK (Pin 1).

Note that there is no method for forcing the right channel to

precede the left channel. The port is configured by pin selec-

tions. The AD1877 can operate in either master or slave mode,

with the data in right-justified, I2S-compatible, Word Clock

controlled or left-justified positions.

The various mode options are pin-programmed with the Slave/

Master Pin (7), the Right/Left Justify Pin (21), and the MSB

Delay Pin (22). The function of these pins is summarized as

follows:

REV. A

–9–

Share Link: