AD1877 Просмотр технического описания (PDF) - Analog Devices
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AD1877 Datasheet PDF : 18 Pages
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AD1877
The AD1877 also features a power-down mode. It is enabled by
the active LO RESET Pin 23 (i.e., the AD1877 is in powerdown
mode while RESET is held LO). The power savings are speci-
fied in the ‘’Specifications’’ section above. The converter is shut
down in the power-down state and will not perform conversions.
The AD1877 will be reset upon leaving the power-down state, and
autocalibration will commence after the RESET pin goes HI.
Power consumption can be further reduced by slowing down the
master clock input (at the expense of input passband width).
Note that a minimum clock frequency, FCLKIN, is specified for
the AD1877.
Tag Overrange Output
The AD1877 includes a TAG serial output (Pin 27) which is
provided to indicate status on the level of the input voltage. The
TAG output is at TTL compatible logic levels. A pair of unsigned
binary bits are output, synchronous with LRCK (MSB then
LSB), that indicate whether the current signal being converted
is: more than 1 dB under full scale; within 1 dB under full scale;
within 1 dB over full scale; or more than 1 dB over full scale.
The timing for the TAG output is shown in TPCs 7 through 16.
Note that the TAG bits are not “sticky,” i.e., they are not peak
reading, but rather change with every sample. Decoding of these
two bits is as follows:
TAG Bits
MSB, LSB
00
01
10
11
Meaning
More Than 1 dB Under Full Scale
Within 1 dB Under Full Scale
Within 1 dB Over Full Scale
More Than 1 dB Over Full Scale
APPLICATIONS ISSUES
Recommended Input Structure
The AD1877 input structure is single-ended to allow the board
designer to achieve a high level of functional integration. The
very simple recommended input circuit is shown in Figure 2.
Note the 1 µF ac coupling capacitor which allows input level
shifting for 5 V only operation, and for autocalibration to
properly null offsets. The 3 dB point of the single-pole antialias
RC filter is 240 kHz, which results in essentially no attenuation
at 20 kHz. Attenuation at 3 MHz is approximately 22 dB, which
is adequate to suppress FS noise modulation. If the analog inputs
are externally ac coupled, then the 1 µF ac coupling capacitors
shown in Figure 2 are not required.
RIGHT
INPUT
LEFT
INPUT
300⍀
300⍀
1F
2.2nF
NPO
1F
2.2nF
NPO
19 VINR
AD1877
10 VINL
Figure 2. Recommended Input Structure for Externally
DC Coupled Inputs
Analog Input Voltage Swing
The single-ended input range of the analog inputs is specified in
relative terms in the “Specifications” section of this data sheet.
The input level at which clipping occurs linearly tracks the voltage
reference level, i.e., if the reference is high relative to the typical
2.25 V, the allowable input range without clipping is corre-
spondingly wider; if the reference is low relative to the typical
2.25 V, the allowable input range is correspondingly narrower.
Thus the maximum input voltage swing can be computed using
the following ratio:
2.25 V (nominal reference voltage)
X Volts (measured reference voltage)
=
3.1 V p −p (nominal voltage swing ) Y Volts (maximum swing without clipping)
Layout and Decoupling Considerations
Obtaining the best possible performance from the AD1877
requires close attention to board layout. Adhering to the follow-
ing principles will produce typical values of 92 dB dynamic
range and 90 dB S/(THD+N) in target systems. Schematics and
layout artwork of the AD1877 Evaluation Board, which implement
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below. The first
two pertain to bypassing and are illustrated in Figure 3.
4.7F
4.7F
470pF
NPO
0.1F
13
14
0.1F
15
16
AGNDL VREFL VREFR AGNDR
470pF 470pF
NPO
NPO
17
18
CAPR2 CAPR1
5V
DIGITAL
0.1F
470pF
NPO
12 CAPL2
11 CAPL1
AGND AVDD
20
9
AD1877
CLKIN 28 OSCILLATOR
DVDD1 DGND1 DGND2 DVDD2
4
5
24
25
0.1F
10nF
10nF
1F
1F
1F
5V
5V
ANALOG DIGITAL
5V
DIGITAL
Figure 3. Recommended Bypassing and Oscillator Circuits
There are two pairs of digital supply pins on opposite sides of
the part (Pins 4 and 5 and Pins 24 and 25). The user should
tie a bypass chip capacitor (10 nF ceramic) in parallel with a
decoupling capacitor (1 µF tantalum) on EACH pair of supply
pins as close to the pins as possible. The traces between these
package pins and the capacitors should be as short and as wide
as possible. This will prevent digital supply current transients
from being inductively transmitted to the inputs of the part.
Use a 0.1 µF chip analog capacitor in parallel with a 1.0 µF
tantalum capacitor from the analog supply (Pin 9) to the analog
ground plane. The trace between this package pin and the
capacitor should be as short and as wide as possible.
The AD1877 should be placed on a split ground plane. The
digital ground plane should be placed under the top end of the
package, and the analog ground plane should be placed under
the bottom end of the package as shown in Figure 4. The split
should be between Pins 8 and 9 and between Pins 20 and 21.
–8–
REV. A
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