AD1877 Просмотр технического описания (PDF) - Analog Devices

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AD1877

Single-Supply 16-Bit ΣΔ Stereo ADC

Analog Devices 

AD1877

S/M RLJUST MSBDLY WCLK

11

1

Output

11

0

Input

10

1

10

0

Output

Output

01

1

01

0

00

1

00

0

Output

Output

Output

Output

BCLK LRCK

Input Input

Input Input

Input Input

Input Input

Output Output

Output Output

Output Output

Output Output

Serial Port Operation Mode

Slave Mode. WCLK frames the data. The MSB is output on the

17th BCLK cycle. Provides right-justified data in slave mode

with a 64 × FS BCLK frequency. See Figure 7.

Slave Mode. The MSB is output in the BCLK cycle after

WCLK is detected HI. WCLK is sampled on the BCLK active

edge, with the MSB valid on the next BCLK active edge. Tying

WCLK HI results in I2S-justified data. See Figure 8.

Slave Mode. Data left-justified with WCLK framing the data.

WCLK rises immediately after an LRCK transition. The MSB is

valid on the first BCLK active edge. See Figure 9.

Slave Mode. Data I2S-justified with WCLK framing the data.

WCLK rises in the second BCLK cycle after an LRCK transi-

tion. The MSB is valid on the second BCLK active edge. See

Figure 10.

Master Mode. Data right-justified. WCLK frames the data,

going HI in the 17th BCLK cycle. BCLK frequency = 64 × FS.

See Figure 11.

Master Mode. Data right-justified + 1. WCLK is pulsed in the

17th BCLK cycle, staying HI for only 1 BCLK cycle. BCLK

frequency = 64 × FS. See Figure 12.

Master Mode. Data left-justified. WCLK frames the data.

BCLK frequency = 64 × FS. See Figure 13.

Master Mode. Data I2S-justified. WCLK frames the data.

BCLK frequency = 64 × FS. See Figure 14.

Serial Port Data Timing Sequences

The RDEDGE input (Pin 6) selects the bit clock (BCLK) polarity.

RDEDGE HI causes data to be transmitted on the BCLK falling

edge and valid on the BCLK rising edge; RDEDGE LO causes

data to be transmitted on the BCLK rising edge and valid on

the BCLK falling edge. This is shown in the serial data output

timing diagrams. The term “sampling” is used generically to

denote the BCLK edge (rising or falling) on which the serial

data is valid. The term “transmitting” is used to denote the

other BCLK edge. The S/M input (Pin 7) selects slave mode (S/

M HI) or master mode (S/M LO). Note that in slave mode,

BCLK may be continuous or gated (i.e., a stream of pulses dur-

ing the data phase followed by periods of inactivity between

channels).

In the master modes, the bit clock (BCLK), the left/right clock

(LRCK), and the word clock (WCLK) are always outputs, gen-

erated internally in the AD1877 from the master clock (CLKIN)

input. In master mode, a LRCK cycle defines a 64-bit “frame.”

LRCK is HI for a 32-bit “field” and LRCK is LO for a 32-bit

“field.”

In the slave modes, the bit clock (BCLK), and the left/right clock

(LRCK) are user-supplied inputs. The word clock (WCLK) is an

internally generated output except when S/M is HI, RLJUST is

HI, and MSBDLY is LO, when it is a user-supplied input which

controls the data position. Note that the AD1877 does not sup-

port asynchronous operation in slave mode; the clocks (CLKIN,

LRCK, BCLK and WCLK) must be externally derived from a

common source. In general, CLKIN should be divided down

externally to create LRCK, BCLK and WCLK.

In the slave modes, the relationship between LRCK and BCLK

is not fixed, to the extent that there can be an arbitrary number

of BCLK cycles between the end of the data transmission and

the next LRCK transition. The slave mode timing diagrams are

therefore simplified as they show precise 32-bit fields and 64-bit

frames.

In two slave modes, it is possible to pack two 16-bit samples in

a single 32-bit frame, as shown in Figures 15 and 16. BCLK,

LRCK, DATA and TAG operate at one half the frequency

(twice the period) as in the 64-bit frame modes. This 32-bit

frame mode is enabled by pulsing the LRCK HI for a minimum

of one BCLK period to a maximum of sixteen BCLK periods.

The LRCK HI for one BCLK period case is shown in Figures

15 and 16. With a one or two BCLK period HI pulse on

LRCK, note that both the left and right TAG bits are output

immediately, back-to-back. With a three to sixteen BCLK period

HI pulse on LRCK, the left TAG bits are followed by one to

fourteen “dead” cycles (i.e., zeros) followed by the right TAG

bits. Also note that WCLK stays HI continuously when the

AD1877 is in the 32-bit frame mode. Figure 15 illustrates the

left-justified case, while Figure 16 illustrates the I2S-justified case.

In all modes, the left and right channel data is updated with the

next sample within the last 1/8 of the current conversion cycle (i.e.,

within the last 4 BCLK cycles in 32-bit frame mode, and within

the last 8 BCLK cycles in 64-bit frame mode). The user must

constrain the output timing such that the MSB of the right channel

is read before the final 1/8 of the current conversion period.

–10–

REV. A

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