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AD13280AZ
(Rev.:Rev0)

Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning

Analog Devices 

AD13280

Parameter

Test Mil

AD13280AZ/BZ

Temp Level Subgroup Min Typ

Max Unit

SPURIOUS-FREE DYNAMIC RANGE1, 8

Analog Input @ 10 MHz

Analog Input @ 21 MHz

Analog Input @ 37 MHz

25°C I

4

Min II

6

Max II

5

25°C I

4

Min II

6

Max II

5

25°C I

4

Min II

6

Max II

5

75

80

70

75

68

75

67

68

56

62

55

56

dBFS

dBFS

dBFS

SINGLE-ENDED ANALOG INPUT

Passband Ripple to 10 MHz

Passband Ripple to 25 MHz

25°C V

25°C V

0.05

dB

0.1

dB

DIFFERENTIAL ANALOG INPUT

Passband Ripple to 10 MHz

Passband Ripple to 25 MHz

25°C V

25°C V

0.3

dB

0.82

dB

TWO-TONE IMD REJECTION9

fIN = 9.1 MHz and 10.1 MHz

f1 and f2 are –7 dB

fIN = 19.1 MHz and 20.7 MHz

f1 and f2 are –7 dB

fIN = 36 MHz and 37 MHz

f1 and f2 are –7 dB

25°C I

4

75

80

dBc

Min II

6

71

Max II

5

75

25°C V

4

77

dBc

25°C V

4

60

dBc

CHANNEL-TO-CHANNEL ISOLATION10

25°C IV

12

90

dB

TRANSIENT RESPONSE

DIGITAL OUTPUTS11

Logic Compatibility

DVCC = 3.3 V

Logic “1” Voltage

Logic “0” Voltage

DVCC = 5 V

Logic “1” Voltage

Logic “0” Voltage

Output Coding

25°C V

Full

I

Full

I

Full

V

Full

V

1, 2, 3

1, 2, 3

25

ns

CMOS

2.5

DVCC – 0.2

V

0.2

0.5 V

DVCC – 0.3

V

0.35

V

Two’s Complement

POWER SUPPLY

AVCC Supply Voltage12

I (AVCC) Current

AVEE Supply Voltage12

I (AVEE) Current

DVCC Supply Voltage12

I (DVCC) Current

ICC (Total) Supply Current per Channel

Power Dissipation (Total)

Power Supply Rejection Ratio (PSRR)

Full

IV

Full

I

Full

IV

Full

I

Full

IV

Full

I

Full

I

Full

I

Full

V

1, 2, 3

1, 2, 3

1, 2, 3

1, 2, 3

1, 2, 3

4.85 5.0

310

–5.25 –5.0

38

3.135 3.3

34

369

3.72

0.01

5.25

338

–4.75

49

3.465

46

433

4.05

V

mA

V

mA

V

mA

mA

W

% FSR/% VS

NOTES

1 All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.

2 Gain tests are performed on AMP-IN-X-1 input voltage range.

3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

4 For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180° out of phase). For single-ended input: +IN = 2 V p-p and = –IN = GND.

5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.

6 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR

is reported in dBFS, related back to converter full scale.

7 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is

reported in dBFS, related back to converter full scale.

8 Analog Input signal at –1 dBFS; SFDR is ratio of converter full scale to worst spur.

9 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.

10Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel.

11 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance.

12 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range

AVCC = 5.0 V to 5.25 V.

Specifications subject to change without notice.

REV. 0

–3–

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