5462-96900 Просмотр технического описания (PDF) - Aeroflex Corporation
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5462-96900 Datasheet PDF : 11 Pages
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Timing Diagrams — SRAM
Read Cycle Timing Diagrams
Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
A0-18
DI/O
tRC
tAA
tOH
Previous Data Valid
Data Valid
Read Cycle 2 (SWE = VIH)
tRC
A0-18
tAA
SCE
OE
DI/O
tACE
tCLZ
SEE NOTE
tOE
tOLZ
SEE NOTE
High Z
tCHZ
SEE NOTE
tOHZ
SEE NOTE
Data Valid
Write Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = VIH)
tWC
A0-18
SCE
tAW
tAH
tCW
tAS
tWP
SWE
DI/O
tWHZ
SEE NOTE
tDW
tDW
tDH
Data Valid
Write Cycle (SCE Controlled, OE = VIH )
tWC
A0-18
SCE
tAW
tAH
tAS
tCW
SWE
DI/O
tWP
tDW
tDH
Data Valid
UNDEFINED
DON’T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
To Device Under Test
CL = 50 pF
Current Source
IOL
VZ ~ 1.5 V (Bipolar Supply)
IOH
Current Source
AC Test Conditions
Parameter
Input Pulse Level
Input Rise and Fall
Input and Output Timing Reference Level
Typical
0 – 3.0
5
1.5
Units
V
ns
V
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
Aeroflex Circuit Technology
4
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
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