5962-9458501H4X Просмотр технического описания (PDF) - Aeroflex Corporation
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5962-9458501H4X Datasheet PDF : 12 Pages
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The usual procedure is to increment the least
significant address lines from A0 through A6
at each write cycle. In this manner a page of
up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning
the relatively long interval programming
cycle.
After the tBLC time out is completed, the
EEPROM begins an internal write cycle.
During this cycle the entire page will be
written at the same time. The internal
programming cycle is the same regardless of
the number of bytes accessed.
byte write sequence of specific data to
specific locations. Power transitions will not
reset the software write protection.
Each 128K byte block of the EEPROM has
independent write protection. One or more
blocks may be enabled and the rest disabled
in any combination. The software write
protection guards against inadvertent writes
during power transitions, or unauthorized
modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent
SOFTWARE DATA PROTECTION
writes to the ACT-E128K32. These are
included to improve reliability during normal
A
A software write protection feature may be operation:
enabled or disabled by the user. When
shipped by Aeroflex Microelectronics, the
A) Vcc Sense
ACT-E128K32 has the feature disabled.
While below 3.8V typical write cycles
Write access to the device is unrestricted.
are inhibited.
To enable software write protection, the user
writes three access code bytes to three
special internal locations. Once write
protection has been enabled, each write to
the EEPROM must use the same three byte
write sequence to permit writing. The write
protection feature can be disabled by a six
B) Write inhibiting
Holding OE low and either CE or WE
high inhibits write cycles.
C) Noise filter
Pulses of <10ns (TYP) on WE or CE
will not initiate a write cycle.
Aeroflex Circuit Technology
5
SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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