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AAT3236

300mA CMOS High Performance LDO

Analog Technology Inc 

AAT3236

300mA CMOS High Performance LDO

First the current duty cycle in percent must be

calculated:

% Peak Duty Cycle: X/100 = 378µs/4.61ms

% Peak Duty Cycle = 8.2%

The LDO Regulator will be under the 100mA load

for 91.8% of the 4.61ms period and have 500mA

peaks occurring for 8.2% of the time. Next, the

continuous nominal power dissipation for the

100mA load should be determined and then multi-

plied by the duty cycle to conclude the actual

power dissipation over time.

PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)

PD(100mA) = (4.2V - 3.3V)100mA + (4.2V x 150µA)

PD(100mA) = 90.6mW

PD(91.8%D/C) = %DC x PD(100mA)

PD(91.8%D/C) = 0.918 x 90.6mW

PD(91.8%D/C) = 83.2mW

The power dissipation for 100mA load occurring for

91.8% of the duty cycle will be 83.2mW. Now the

power dissipation for the remaining 8.2% of the

duty cycle at the 500mA load can be calculated:

PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)

PD(500mA) = (4.2V - 3.3V)500mA + (4.2V x 150µA)

PD(500mA) = 450.6mW

PD(8.2%D/C) = %DC x PD(500mA)

PD(8.2%D/C) = 0.082 x 450.6mW

PD(8.2%D/C) = 37mW

The power dissipation for 500mA load occurring for

8.2% of the duty cycle will be 37mW. Finally, the two

power dissipation levels can summed to determine

the total true power dissipation under the varied load.

PD(total) = PD(100mA) + PD(500mA)

PD(total) = 83.2mW + 37mW

PD(total) = 120.2mW

The maximum power dissipation for the AAT3236

operating at an ambient temperature of 25°C is

526mW. The device in this example will have a

total power dissipation of 120.2mW. This is well

within the thermal limits for safe operation of the

device.

Printed Circuit Board Layout

Recommendations

In order to obtain the maximum performance from

the AAT3236 LDO regulator, very careful attention

must be considered in regard to the printed circuit

board (PCB) layout. If grounding connections are

not properly made, power supply ripple rejection,

low output self noise and transient response can be

compromised.

Figure 18 shows a common LDO regulator layout

scheme. The LDO Regulator, external capacitors

(CIN, COUT and CBYP) and the load circuit are all

connected to a common ground plane. This type of

layout will work in simple applications where good

power supply ripple rejection and low self noise are

not a design concern. For high performance appli-

cations, this method is not recommended.

VIN

IIN

DC INPUT

VIN

LDO VOUT

Regulator

EN

BYP

GND

CIN

IRIPPLE

IGND

IBYP + noise

ILOAD

CBYP

GND

LOOP

CBYP

COUT

GND

RTRACE

RTRACE

RTRACE

RTRACE

ILOAD return + noise and ripple

Figure 18: Common LDO Regulator Layout with CBYP Ripple feedback loop

RLOAD

12

3236.2001.11.0.9

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