CS5542 Просмотр технического описания (PDF) - Cirrus Logic

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CS5542

22-Bit, Multi-Channel ∆Σ ADC Chip Set

Cirrus Logic 

CS5542 CS5543

SLOT6

(Previous

Frame)

SLOT7

(Previous

Frame)

SLOT0

SLOT1

SLOT2

SLOT3

MCLK

(2048 x OWR)

FSYNC

(Modulator

Fs Rate)

ONE FRAME

8 CHANNELS

4 SLOT-PAIRS

CHIP #4 ACTIVE

(Previous Frame)

CHIP #1 ACTIVE

SLOT PAIR #1

CHIP #2 ACTIVE

SLOT PAIR #2

SLOT4

SLOT5 SLOT6

SLOT7

CHIP #3 ACTIVE

SLOT PAIR #3

CHIP #4 ACTIVE

SLOT PAIR #4

MDATA3:0

L

R

L

R

L

R

L

R

L

R

INTER-CHIP

HANDOFF POINT

CS5542 Frame Timing Overview

ONE SLOT

PAIR

MCLK

MDATA[3:0]

HI-Z STATE (Note 1)

LEFT

DATA

RIGHT

DATA

HI-Z STATE (Note 1)

Notes

1

Hi-Z State shown as intermediate level for clarity only.

Bus capacitance would normally maintain valid logic one

level during Hi-Z until next time slot pair becomes active.

CS5542 MDATA3-MDATA0 Output Timing Characteristics

DS109PP2

3

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