A64S06162A Просмотр технического описания (PDF) - AMIC Technology

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A64S06162A

16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory

AMIC Technology 

Preliminary

PAGE MODE WRITE CYCLE (/PD = VIH)

tWC

Address(A2 – A19)

Page Address(A0 – A1)

/CS

tAS(1)

/UB,/LB

tCW(3)

tBW

tPWC

/WE

DATA IN

tWP(1)

tDW tDH

tPDW tPDH

DATA OUT

High-Z

A64S06162A

tP

tPDW tPDH

Notes (PAGE MODE WRITE CYCLE) :

1. A write occurs during the overlap of a low /CS and low /WE.

A write begins at the latest transition among /CS going low in initial page mode .

A write end at the earliest transition among /CS going high and Page Address transition.

tWP is measured from the beginning of write to the end of write in initial page access.

2. tPWC is measured from Page Address trasition (After initial page access)

to Page Address transition or /CS going high.

2. tCW is measured from the later of /CS going low to the end of write in initial page access.

3. tAS is measured from the address valid to the beginning of write.

4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.

5. tP (precharge time) should be guaranteed for new Page Address.

6. After initial page access is accomplished, the page mode operation provides fast read access speed of

random locations within that page

(May, 2005, Version 0.0)

11

AMIC Technology, Corp.

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