A6818(2008) Просмотр технического описания (PDF) - Allegro MicroSystems
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A6818 Datasheet PDF : 7 Pages
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A6818
DABiC-IV 32-Bit Serial Input
Latched Source Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................................ 25 ns
C. Clock Pulse Width, tw(CH) ................................................. 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns
E. Strobe Pulse Width, tw(STH) .............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Significantly
higher speeds are attainable.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK in-
put pulse. On succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the
CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as long
as the STROBE is held high. Applications where the latches are
bypassed (STROBE tied high) will require that the BLANKING
input be high during serial data entry.
When the BLANKING input is high, the output source driv-
ers are disabled (OFF); the pnp active pull-down sink drivers are
ON. The information stored in the latches is not affected by the
BLANKING input. With the BLANKING input low, the outputs
are controlled by the state of their respective latches.
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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