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A43L2632V-6

1M X 32 Bit X 4 Banks Synchronous DRAM

AMIC Technology 

A43L2632

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address BS1 BS0 A11 A10 A9

A8 A7 A6 A5 A4 A3 A2 A1

A0

Function 0

0

RFU

W.B.L

TM

CAS Latency

BT

Burst Length

(Note 3)

(Note 2) (Note 1)

Test Mode

A8 A7

Type

0 0 Mode Register Set

01

Vendor

10

11

Use

Only

Write Burst Length

A9

Length

0

Burst

1

Single Bit

CAS Latency

Burst Type

Burst Length

A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0

0 0 0 Reserved 0 Sequential 0 0 0

1

001

1

1 Interleave 0 0 1

2

010

2

010

4

BT=1

1

2

4

011

3

011

8

8

1 0 0 Reserved

1 0 0 Reserved Reserved

1 0 1 Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved

1 1 0 Reserved Reserved

1 1 1 Reserved

1 1 1 256(Full) Reserved

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. BS0,BS1 must be 0,0 to select the Mode Register (vs. the Extended Mode Register).

PRELIMINARY (January, 2005, Version 0.0)

11

AMIC Technology, Corp.

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