82443MX Просмотр технического описания (PDF) - Intel

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82443MX

82443MX PCIset

Intel 

82443MX PCIset

CONTENTS

PAGE

1. INTRODUCTION ...................................................................................................................................... 1

1.1 82440MX Chipset Feature Summary ............................................................................................. 1

1.2 82440MX Chipset Features ............................................................................................................ 2

2. ARCHITECTURE OVERVIEW ................................................................................................................. 5

3. REFERENCES ......................................................................................................................................... 6

4. SIGNAL DESCRIPTION AND PIN STATES............................................................................................. 7

4.1 Pin List ........................................................................................................................................... 7

4.1.1 Signal Description ............................................................................................................. 8

4.1.2 Power and Ground Pins .................................................................................................. 22

4.2 GPIO Definition............................................................................................................................. 23

4.3 Power Rail Overview .................................................................................................................... 26

4.4 Power-Up State Initial Value ......................................................................................................... 27

4.5 Power-On Reset Pin Values ......................................................................................................... 27

4.6 Power-Up/Reset Strap Options..................................................................................................... 35

4.7 CPU Reset ................................................................................................................................... 37

5. POWER PLANES................................................................................................................................... 38

5.1 Overview ...................................................................................................................................... 38

5.2 RTC Power Plane ......................................................................................................................... 38

5.3 Resume Power Plane ................................................................................................................... 38

6. SYSTEM ADDRESS MAP...................................................................................................................... 40

6.1 Addressable Memory Support ...................................................................................................... 40

6.2 Memory Map................................................................................................................................. 40

6.2.1 Compatibility Area........................................................................................................... 42

6.2.1.1

DOS Area (00000h-9FFFh; 0 - 640 KB) .................................................... 43

6.2.1.2

Video Buffer Area (A0000h-BFFFFh; 640 - 768 KB).................................. 43

6.2.1.3

Expansion Area (C0000h-DFFFFh; 768 - 896 KB) .................................... 43

6.2.1.4

Extended System BIOS Area (E0000h-EFFFFh; 896 - 960 KB)................ 43

6.2.1.5

System BIOS Area (F0000h-FFFFFh; 960 KB - 1 MB).............................. 43

6.2.2 Extended Memory Area .................................................................................................. 43

6.2.2.1

Main DRAM Address Range (0010_0000h to Top of Main Memory) ......... 44

6.2.2.2

Extended SMRAM Address Range (Top of Main Memory - TSEG_SZ to

Top of Main Memory) ................................................................................ 44

iii

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