82443MX Просмотр технического описания (PDF) - Intel

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82443MX

82443MX PCIset

Intel 

82443MX PCIset

 Refresh mechanism

Supports CAS-before-RAS

Self Refresh during C3, POS and Suspend mode (STR)

 Enhanced Open Page Arbitration SDRAM paging scheme

 Support for DIMM serial Presence Detect scheme via SMBus interface

 Support for DRAM power throttling

PCI Bus interface

 PCI Rev. 2.2, 3.3V, 33 MHz interface compliant

 Asynchronous coupling to the host bus/core frequency

 PCI parity generation support

 CPU-to-PCI write assembly of full/partial line writes

 Combines back-to-back sequential CPU-to-PCI memory writes into PCI burst writes

 Data streaming support from PCI to DRAM (~120 MB/s for writes, ~100MB/s for reads)

 Delayed transaction support for PCI reads which cannot be serviced immediately

 Supports concurrent CPU, PCI transactions to main memory

 Integrated PCI arbiter with multi-transaction arbitration mechanism

 4 PCI bus masters support for combination of Graphic, LAN, CardBus, Audio, Modem

 Overall arbitration scheme and concurrency

 Distributed arbitration model for optimum concurrency support

 Concurrent operations of CPU, PCI supported via dedicated arbitration and data buffering logic

PCI arbiter

CPU bus arbiter

DRAM arbitration for managing multiple request queues

Internal DRAM controller arbitration between data requests and Refresh requests

 Overall data buffering

 Distributed data buffering model for optimum concurrency

 DRAM write buffer with read-around-write capability

 Dedicated CPU-DRAM, PCI-DRAM read buffers

 CPU-PCI deferred transaction buffering (bi-directional for reads and writes)

 Delayed transaction read buffering for PCI path

System peripherals

 Interrupt controller

 15 interrupts with dual cascaded 8259

 Serial interrupt input

 System timer, speaker tone generator

 DMA controller supports the following:

Dual cascaded 8237

DDMA

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