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MB40C360PFV Просмотр технического описания (PDF) - Fujitsu

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MB40C360PFV
Fujitsu
Fujitsu Fujitsu
MB40C360PFV Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MB40C360
s PIN ASSIGNMENT
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
CLK
(TOP VIEW)
1
2 (LSB)
3
4
5
6
7
8
9
10
11 (MSB)
12
24
AVDD
23
AVSS
22
CE
21
VRB
20
VINA
19
VRT
18
AVDD
17
AVSS
16
OE
15
AVSS
14
AVDD
13
DVDD
(FPT-24P-M03)
s PIN DESCRIPTION
Pin No.
14, 18, 24
13
15, 17, 23
1
2, 3, 4, 5, 6
7, 8, 9, 10, 11
12
20
19
21
22
16
Symbol
AVDD
DVDD
AVSS
DVSS
D0 to D9
CLK
VINA
VRT
VRB
CE
OE
Description
Analog power supply (+3.0 V)
Digital power supply (+3.0 V)
Analog power supply ground pin (0 V)
Digital power supply ground pin (0 V)
Digital output pin (D0: LSB, D9: MSB)
Clock input pin (3 V CMOS input)
A/D converter analog input pin
Input range is VRB to VRT (0 V to 2.0 V: standard)
Reference voltage input pin on top side (2.0 V: standard)
Reference voltage input pin on bottom side (0 V: standard)
Chip enable input pin
Input high signal brings standby state. Input low signal brings operation state.
Output enable input pin
Input high signal readies digital output high-impedance state.
Input low signal induces digital output state.
Note: The values in parentheses are standard.
2

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