70P2352-IGT Просмотр технического описания (PDF) - Unspecified
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70P2352-IGT Datasheet PDF : 42 Pages
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
ADDRESS N-2: ADVANCED TRANSMIT CONTROL REGISTER 1
BIT NAME TYPE
DFLT
VALUE
DESCRIPTION
7:1
--
R/W 0000000 Reserved.
0 TXEQ R/W
Transmit Fixed Equalizer Enable:
When enabled, compensates for between 0.75m and 1.5m of FR4 trace
0
to the serial LVPECL data inputs SIxDP/N
0: Normal Operation
1: Enable equalizer
ADDRESS N-3: ADVANCED TRANSMIT CONTROL REGISTER 0
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:3
--
R/W 10101 Reserved.
2:1 BST[1:0] R/W
0
FLBK R/W
Transmit Driver Amplitude Boost:
Adds roughly 5% or 10% of boost to the CMI output. Limits not tested
during production test.
00
00 : Normal amplitude
01 : 5% boost
10 : Reserved
11 : 10% boost
Full Remote (digital) Loopback Enable:
When enabled the recovered receive data is decoded and looped back
0
to the transmit clock recovery unit exercising the entire receive and
transmit paths.
NOTE: Must be used in conjunction with Serial Plesiochronous Mode or
Serial Loop-Timing Mode.
ADDRESS N-4: MODE CONTROL REGISTER 2
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
Line Interface Mode Selection:
7
CMI
R/W
1
0: Optical fiber (LVPECL, NRZ). CMI ENDEC and line driver are
disabled. Use RXxP/N and ECLxP/N pins for line interface.
1: Coaxial cable (CMI encoded). CMI ENDEC enabled. Optical
(NRZ) interface disabled. Use RXxP/N and CMIxP/N pins for
line interface.
6:0
--
R/W XX00000 Reserved.
Page: 14 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
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