74VHC393 Просмотр технического описания (PDF) - Fairchild Semiconductor
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74VHC393 Datasheet PDF : 8 Pages
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March 1993
Revised February 2005
74VHC393
Dual 4-Bit Binary Counter
General Description
The VHC393 is an advanced high speed CMOS 4-bit
Binary Counter fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. It contains two independent counter cir-
cuits in one package, so that counting or frequency division
of 8 binary bits can be achieved with one IC. This device
changes state on the negative going transition of the
CLOCK pulse. The counter can be reset to “0” (Q0–Q3
“L”) by a HIGH at the CLEAR input regardless of other
inputs.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: fMAX 170 MHz (typ) at TA 25qC
s Low power dissipation: ICC 4 PA (max) at TA 25qC
s High noise immunity: VNIH VNIL 28% VCC (min)
s Power down protection is provided on all inputs
s Pin and function compatible with 74HC393
Ordering Code:
Order Number
Package
Number
Package Description
74VHC393M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC393SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC393MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC393MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1)
Wide
74VHC393N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
CLR1, CLR2
CP1, CP2
QA, QB, QC, QD
Description
Clear Inputs
Clock Pulse Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation DS011571
www.fairchildsemi.com
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