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74LVT10D

3.3V Triple 3-input NAND gate

Philips Electronics 

Philips Semiconductors

3.3V Triple 3-input NAND gate

Product specification

74LVT10

QUICK REFERENCE DATA

LOGIC SYMBOL (IEEE/IEC)

SYMBOL PARAMETER

CONDITIONS

Tamb = 25°C;

GND = 0V

Propagation

tPLH delay

tPHL An, Bn, Cn

to Yn

CL = 50pF;

VCC = 3.3V

CIN

Input

capacitance

VI = 0V or 3.0V

TYPICAL UNIT

3.8

3.3

ns

2

pF

1

&

2

12

13

3

4

6

5

ICCL

Total supply

current

Outputs Low;

VCC = 3.6V

1

mA

9

10

8

PIN CONFIGURATION

11

A0 1

B0 2

A1 3

B1 4

C1 5

Y1 6

GND 7

14 VCC

13 C0

12 Y0

11 C2

10 B2

9 A2

8 Y2

SA00346

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

NAME AND FUNCTION

1, 2, 3, 4, 5,

9, 10, 11, 13

An, Bn,

Cn

Data inputs

LOGIC DIAGRAM

VCC = Pin 14

GND = Pin 7

1

A0

2

B0

13

C0

3

A1

4

B1

5

C1

9

A2

10

B2

11

C2

SV00059

12

Y0

6

Y1

8

Y2

SA00348

6, 8, 12

7

14

Yn

GND

VCC

Data outputs

Ground (0V)

Positive supply voltage

LOGIC SYMBOL

1 2 13 3 4 5 9 10 11

A0 B0 C0 A1 B1 C1 A2 B2 C2

VCC = Pin 14

GND = Pin 7

Y0 Y1 Y2

12 6 8

SA00347

FUNCTION TABLE

INPUTS

Dna

Dnb

Dnc

L

L

L

L

L

H

L

H

L

L

H

H

H

L

L

H

L

H

H

H

L

H

H

H

NOTES:

H = High voltage level

L = Low voltage level

OUTPUTS

Qn

H

H

H

H

H

H

H

L

ORDERING INFORMATION

PACKAGES

14-Pin Plastic SO

14-Pin Plastic SSOP

14-Pin Plastic TSSOP

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74LVT10 D

74LVT10 DB

74LVT10 PW

NORTH AMERICA

74LVT10 D

74LVT10 DB

74LVT10PW DH

DWG NUMBER

SOT108-1

SOT337-1

SOT402-1

1996 May 10

2

853–1832 16801

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