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74LVC3G07

Triple buffer with open-drain output

Philips Electronics 

74LVC3G07

Triple buffer with open-drain output

Rev. 03 — 01 February 2005

Product data sheet

1. General description

The 74LVC3G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device

and superior to most advanced CMOS compatible TTL families.

Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry

disables the output, preventing the damaging backflow current through the device when it

is powered down.

The 74LVC3G07 provides three non-inverting buffers.

The output of the device is an open drain and can be connected to other open-drain

outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

2. Features

s Wide supply voltage range from 1.65 V to 5.5 V

s 5 V tolerant input/output for interfacing with 5 V logic

s High noise immunity

s Complies with JEDEC standard:

x JESD8-7 (1.65 V to 1.95 V)

x JESD8-5 (2.3 V to 2.7 V)

x JESD8-B/JESD36 (2.7 V to 3.6 V).

s ESD protection:

x HBM EIA/JESD22-A114-B exceeds 2000 V

x MM EIA/JESD22-A115-A exceeds 200 V.

s −24 mA output drive (VCC = 3.0 V)

s CMOS low power consumption

s Latch-up performance exceeds 250 mA

s Direct interface with TTL levels

s Inputs accept voltages up to 5 V

s Multiple package options

s Specified from −40 °C to +85 °C and −40 °C to +125 °C.

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