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74LV4020 Datasheet PDF : 20 Pages
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Philips Semiconductors
74LV4020
14-stage binary ripple counter
Table 8: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9.
Symbol Parameter
Conditions
Min Typ Max Unit
trec
recovery time
MR to CP
see Figure 8
fmax
maximum input clock frequency
CPD
power dissipation capacitance
Tamb = −40 °C to +125 °C
tPHL,
tPLH
propagation delay
CP to Q0
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 3.3 V; CL = 15 pF
per gate; VI = GND to VCC
see Figure 7
-
22
16
13
10
14
19
24
36
-
[2] -
10
-
5
-
4
-
3
-
2
-
60
-
76
-
94
-
112 -
100 -
20
-
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
pF
Qn to Q(n+1)
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
-
-
-
ns
-
-
54
ns
-
-
38
ns
-
-
32
ns
-
-
22
ns
tPHL
propagation delay
MR to Qn
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 8
-
-
-
ns
-
-
37
ns
-
-
26
ns
-
-
22
ns
-
-
15
ns
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
ns
-
-
55
ns
-
-
39
ns
-
-
32
ns
-
-
22
ns
74LV4020_1
Product data sheet
Rev. 01 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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