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74HC4059N

Programmable divide-by-n counter

Philips Electronics 

Philips Semiconductors

Programmable divide-by-n counter

Product specification

74HC/HCT4059

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

HC

HCT

tPHL/ tPLH

propagation delay CP to Q

CL = 15 pF; VCC = 5 V 18

20

fmax

maximum clock frequency

40

40

CI

input capacitance

3.5

3.5

CPD

power dissipation capacitance per package notes 1 and 2

30

32

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

UNIT

ns

MHz

pF

pF

ORDERING INFORMATION

TYPE

NUMBER

74HC4059N3;

74HCT4059N3

74HC4059N;

74HCT4059N

74HC4059D;

74HCT4059D

NAME

DIP24

DIP24

SO24

PACKAGE

DESCRIPTION

plastic dual in-line package; 24 leads (300 mil)

plastic dual in-line package; 24 leads (600 mil)

plastic small outline package; 24 leads; body width 7.5 mm

VERSION

SOT222-1

SOT101-1

SOT137-1

1998 Jul 08

4

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