74HC4024(2004) Просмотр технического описания (PDF) - Philips Electronics
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74HC4024 Datasheet PDF : 18 Pages
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Philips Semiconductors
13. Waveforms
74HC4024
7-stage binary ripple counter
MR input
VM
tW
CP input
tPHL
Q0 or Qn
output
1/fmax
trem
tW
tPLH
tTLH
VM
tPHL
VM
tTHL
001aab910
Fig 6.
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) removal time.
VM = 0.5 × VI.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock
pulse width, the output transition times and the maximum clock frequency
PULSE
VI
GENERATOR
VCC
VO
D.U.T.
RT
CL
mna101
Fig 7.
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Load circuitry for switching times
Table 9:
Supply
VCC
2.0 V
4.5 V
6.0 V
5.0 V
Test data
Input
VI
VCC
VCC
VCC
VCC
tr, tf
6 ns
6 ns
6 ns
6 ns
Load
CL
50 pF
50 pF
50 pF
15 pF
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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