74F579 Просмотр технического описания (PDF) - Fairchild Semiconductor

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74F579

8-Bit Bidirectional Binary Counter with 3-STATE Outputs

Fairchild Semiconductor 

Unit Loading/Fan Out

Pin Names

Description

I/O0–I/O7

PE

U/D

MR

SR

CEP

CET

CS

OE

CP

TC

Data Inputs or

3-STATE Outputs

Parallel Enable Input (Active LOW)

Up-Down Count Control Input

Master Reset Input (Active LOW)

Synchronous Reset Input (Active LOW)

Count Enable Parallel Input (Active LOW)

Count Enable Trickle Input (Active LOW)

Chip Select Input Active (Active LOW)

Output Enable Input (Active LOW)

Clock Pulse Input (Active Rising Edge)

Terminal Count Output (Active LOW)

U.L.

HIGH/LOW

3.5/0.333

75/15

0.25/0.333

0.25/0.333

0.25/0.333

0.25/0.333

0.25/0.333

0.25/0.333

0.25/0.333

0.25/0.333

0.25/0.333

25/12.5

Input IIH/IIL

Output IOH/IOL

70 µA/−0.2 mA

−3 mA/24 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

5 µA/−0.2 mA

−1 mA/5 mA

Function Table

MR SR CS PE CEP CET U/D OE CP

Function

X X H X X X X X X I/Oa to I/Oh in High Z (PE Disabled)

X X L H X X X H X I/Oa to I/Oh in High Z

X X L H X X X L X Flip-Flop Outputs Appear on I/O Lines

L

H

H

H

H

H

H

X

L

H

H

H

H

H

XX

XX

LL

(Not LL)

(Not LL)

(Not LL)

(Not LL)

X

X

X

H

X

L

L

X

X

X

X

H

L

L

X

X

X

X

X

H

L

X

X

X

X

X

X

X

X

Asynchronous Reset for all Flip-Flops

Synchronous Reset for all Flip-Flops

Parallel Load all Flip-Flops

Hold

Hold (TC Held HIGH)

Count Up

Count Down

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW to HIGH Clock Transition

Not LL = CS and PE should never both be LOW voltage level at the same time.

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