74F161ASJ Просмотр технического описания (PDF) - Fairchild Semiconductor

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74F161ASJ

Synchronous Presettable Binary Counter

Fairchild Semiconductor 

Logic Symbols

74F161A

IEEE/IEC

74F163A

IEEE/IEC

74F161A

Unit Loading/Fan Out

74F163A

Pin Names

Description

CEP

Count Enable Parallel Input

CET

Count Enable Trickle Input

CP

Clock Pulse Input (Active Rising Edge)

MR (74F161A) Asynchronous Master Reset Input (Active LOW)

SR (74F163A) Synchronous Reset Input (Active LOW)

P0–P3

PE

Parallel Data Inputs

Parallel Enable Input (Active LOW)

Q0–Q3

TC

Flip-Flop Outputs

Terminal Count Output

U.L.

HIGH/LOW

1.0/1.0

1.0/2.0

1.0/1.0

1.0/1.0

1.0/2.0

1.0/1.0

1.0/2.0

50/33.3

50/33.3

Input IIH/IIL

Output IOH/IOL

20 µA/−0.6 mA

20 µA/−1.2 mA

20 µA/−0.6 mA

20 µA/−0.6 mA

20 µA/−1.2 mA

20 µA/−0.6 mA

20 µA/−1.2 mA

−1 mA/20 mA

−1 mA/20 mA

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