74AC251SJ Просмотр технического описания (PDF) - Fairchild Semiconductor
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74AC251SJ Datasheet PDF : 9 Pages
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Functional Description
Truth Table
This device is a logical implementation of a single-pole, 8-
position switch with the switch position controlled by the
Inputs
Outputs
state of three Select inputs, S0, S1, S2. Both true and com-
OE
S2
S1
S0
Z
Z
plementary outputs are provided. The Output Enable input
(OE) is active LOW. When it is activated, the logic function
H
X
X
X
Z
Z
provided at the output is:
Z = OE • (I0 • S0 • S1 • S2 + I1• S0 • S1 • S2 +
I2 • S0 • S1 • S2 + I3 • S0 • S1 • S2 +
I4 • S0 • S1 • S2 + I5 • S0 • S1 • S2 +
I6 • S0 • S1 • S2 + I7 • S0 • S1 • S2)
L
L
L
L
I0
I0
L
L
L
H
I1
I1
L
L
H
L
I2
I2
L
L
H
H
I3
I3
When the Output Enable is HIGH, both outputs are in the
L
H
L
L
I4
I4
high impedance (High Z) state. This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
together. When the outputs of the 3-STATE devices are
L
H
L
H
I5
I5
L
H
H
L
I6
I6
tied together, all but one device must be in the high imped-
ance state to avoid high currents that would exceed the
L
H
H
H
I7
I7
maximum ratings. The Output Enable signals should be
H = HIGH Voltage Level
L = LOW Voltage Level
designed to ensure there is no overlap in the active-LOW X = Immaterial
portion of the enable voltages.
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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