74ABT657 Просмотр технического описания (PDF) - NXP Semiconductors.
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74ABT657 Datasheet PDF : 17 Pages
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NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter
Conditions
tPLH
LOW to HIGH
An to Bn or Bn to An; see Figure 6
propagation delay An to PARITY; see Figure 5 and 6
ODD/EVEN to PARITY and ERROR;
see Figure 5 and 6
Bn to ERROR; see Figure 5 and 6
PARITY to ERROR; see Figure 5 and 6
tPHL
HIGH to LOW
An to Bn or Bn to An; see Figure 6
propagation delay An to PARITY; see Figure 5 and 6
ODD/EVEN to PARITY and ERROR;
see Figure 5 and 6
Bn to ERROR; see Figure 5 and 6
PARITY to ERROR; see Figure 5 and 6
tPZH
OFF-state to HIGH see Figure 7 and 8
propagation delay
tPZL
OFF-state to LOW see Figure 7 and 8
propagation delay
tPHZ
HIGH to OFF-state see Figure 7 and 8
propagation delay
tPLZ
LOW to OFF-state see Figure 7 and 8
propagation delay
25 °C; VCC = 5.0 V −40 °C to +85 °C; Unit
VCC = 5.0 V ± 0.5 V
Min Typ Max Min
Max
1.1 2.5 4.1 1.1
4.6 ns
2.5 5.1 6.7 2.5
8.1 ns
1.7 3.5 4.6 1.7
5.3 ns
3.9 7.3 10.2 3.9
2.7 4.5 5.9 2.7
1.2 3.0 3.9 1.2
2.8 5.0 7.4 2.8
1.9 3.7 5.1 1.9
12.3 ns
7.7 ns
4.3 ns
8.9 ns
5.8 ns
4.0 7.9 10.5 4.0
3.2 5.2 6.7 3.2
[1] 1.3 3.6 5.5
1.3
12.9 ns
8.1 ns
6.5 ns
[1] 1.9 4.2 5.3
1.9
6.5 ns
2.4 3.6 5.6 2.4
6.2 ns
2.2 3.4 7.3 2.2
7.8 ns
[1] These delay times reflect the 3-state recovery time only and do not include the delay through the buffers and the parity check circuitry
which affect the ERROR output. To ensure valid information at the ERROR pin, time must be allowed for the signal to propagate
through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output. Valid data at the
ERROR pin ≥ (B to A) + (A to PARITY).
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
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