HM628128DLP-5 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HM628128DLP-5 Datasheet PDF : 20 Pages
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HM628128D Series
AC Characteristics (Ta = –20 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: VIL = 0.8 V, VIH = 2.4 V
• Input rise and fall time: 5 ns
• Input timing reference levels: 1.5 V
• Output timing reference level: 1.5 V
• Output load: 1 TTL Gate+ CL (100 pF) (HM628128D-7)
1 TTL Gate+ CL (50 pF) (HM628128D-5)
(Including scope and jig)
Read Cycle
HM628128D
-5
-7
Parameter
Symbol Min
Max
Min
Read cycle time
t RC
55
—
70
Address access time
t AA
—
55
—
Chip select access time
t ACS1
—
55
—
t ACS2
—
55
—
Output enable to output valid
t OE
—
30
—
Output hold from address change tOH
10
—
10
Chip selection to output in low-Z
t CLZ1
10
—
10
t CLZ2
10
—
10
Output enable to output in low-Z
t OLZ
5
—
5
Chip deselection to output in high-Z tCHZ1
0
20
0
t CHZ2
0
20
0
Output disable to output in high-Z tOHZ
0
20
0
Max
Unit
Notes
—
ns
70
ns
70
ns
70
ns
35
ns
—
ns
—
ns
2, 3
—
ns
2, 3
—
ns
2, 3
25
ns
1, 2, 3
25
ns
1, 2, 3
25
ns
1, 2, 3
7
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