P4C148-10PC Просмотр технического описания (PDF) - Performance Semiconductor
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P4C148-10PC Datasheet PDF : 6 Pages
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P4C148/P4C149
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-10
Min Max
t
RC
Read Cycle Time
tAA Address Access Time
tAC† Chip Enable Access Time
(P4C148)
10
10
10
tAC* Chip Select Access Time
8
(P4C149)
tOH Output Hold from Address
3
Change
tLZ* Chip Enable to Output in Low Z 2
tHZ* Chip Disable to Output in High Z
4
tRCS Read Command Setup Time
0
tRCH Read Command Hold Time
0
tPU† Chip Enable to Power Up Time 0
tPD† Chip Disable to Power Down
10
Time
-12
Min Max
12
12
12
10
3
2
5
0
0
0
12
-15
-20
-25
-35
Min Max Min Max Min Max Min Max
15
20
25
35
15
20
25
35
15
20
25
35
12
14
15
20
3
3
3
3
2
2
2
2
6
8
10
14
0
0
0
0
0
0
0
0
0
0
0
0
15
20
25
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF READ CYCLE NO. 1(5)
(8)
t RC
ADDRESS
DATA OUT
t AA
t OH
PREVIOUS DATA VALID
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
t RC
CE
DATA OUT
WE
VCC SUPPLY I CC
CURRENT I SB
(P4C148 ONLY)
(7)
t LZ
t AC
t RCS
t PU
t HZ (7)
DATA VALID
t RCH
HIGH IMPEDANCE
t PD
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
21
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