AD5313ARUZ Просмотр технического описания (PDF) - Analog Devices
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AD5313ARUZ Datasheet PDF : 28 Pages
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AD5303/AD5313/AD5323
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Output Voltage Settling Time
AD5303
AD5313
AD5323
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A, B Version3
Min Typ
Max
6
8
7
9
8
10
0.7
12
0.10
0.01
0.01
200
−70
Unit Conditions/Comments
VREF = VDD = 5 V
μs ¼ scale to ¾ scale change (0x40 to 0xc0)
μs ¼ scale to ¾ scale change (0x100 to 0x300)
μs ¼ scale to ¾ scale change (0x400 to 0xc00)
V/μs
nV-s 1 LSB change around major carry
(011 . . . 11 to 100 . . . 00)
nV-s
nV-s
nV-s
kHz VREF = 2 V ± 0.1 V p-p, unbuffered mode
dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range for Version A and Version B: −40°C to +105°C.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t124, 5
t134, 5
t145
t155
Limit at TMIN, TMAX
(A, B Version)
33
13
13
0
5
4.5
0
100
20
20
20
5
20
0
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
CLR pulse width
SCLK falling edge to SDO invalid
SCLK falling edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 4 and Figure 5.
4 These are measured with the load circuit of Figure 4.
5 Daisy-chain mode only (see Figure 47).
Rev. B | Page 6 of 28
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