AD5313ARUZ Просмотр технического описания (PDF) - Analog Devices
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AD5313ARUZ Datasheet PDF : 28 Pages
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AD5303/AD5313/AD5323
Parameter 2
LOGIC INPUTS5
Input Current
A Version1
B Version1
Min Typ
Max Min Typ
Max Unit
±1
±1 μA
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
LOGIC OUTPUT (SDO)5
2.4
2.1
2.0
2
0.8
0.6
0.5
2.4
2.1
2.0
3.5
2
0.8 V
0.6 V
0.5 V
V
V
V
3.5 pF
VDD = 5 V ± 10%
Output Low Voltage
Output High Voltage
4.0
VDD = 3 V ± 10%
Output Low Voltage
Output High Voltage
2.4
Floating-State Leakage Current
Floating-State Output
3
Capacitance
0.4
4.0
0.4
2.4
1
3
0.4 V
V
0.4 V
V
1
μA
pF
POWER REQUIREMENTS
VDD
2.5
IDD (Normal Mode)
5.5 2.5
5.5 V
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
300
450
230
350
300
450 μA
230
350 μA
IDD (Full Power-Down)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
0.2
1
0.05
1
0.2
1
μA
0.05
1
μA
Conditions/Comments
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
ISINK = 2 mA
ISOURCE = 2 mA
ISINK = 2 mA
ISOURCE = 2 mA
DCEN = GND
DCEN = GND
IDD specification is valid for all DAC codes
Both DACs active and excluding load
currents
Both DACs in unbuffered mode;
VIH = VDD and VIL = GND; in buffered
mode, extra current is typically x μA
per DAC, where x = 5 μA + VREF/RDAC
1 Temperature range for Version A, Version B: −40°C to +105°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981).
5 Guaranteed by design and characterization, not production tested.
6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD
and offset plus gain error must be positive.
Rev. B | Page 4 of 28
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