AD5313ARU-REEL7(RevA) Просмотр технического описания (PDF) - Analog Devices

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производитель

AD5313ARU-REEL7
(Rev.:RevA)

2.5 V to 5.5 V, 230 μ
A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs

Analog Devices 

AD5303/AD5313/AD5323

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1

CLR

Active Low Control Input that Loads All Zeros to Both Input and DAC Registers.

2

LDAC

Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC Registers.

Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data.

This allows simultaneous update of both DAC outputs

3

VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled

to GND.

4

VREFB

Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or an

unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in

unbuffered mode and from 1 V to VDD in buffered mode.

5

VREFA

Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or an

unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered

mode and from 1 V to VDD in buffered mode.

6

VOUTA

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

7

BUF A

Control Pin that Controls whether the Reference Input for DAC A is Unbuffered or Buffered. If this pin is

tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

8

BUF B

Control Pin that Controls whether the Reference Input for DAC B is Unbuffered or Buffered. If this pin is

tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

9

DCEN

This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a

daisy-chain. The pin should be tied low if it is being used in standalone mode.

10

PD

Active Low Control Input that Acts as a Hardware Power-Down Option. This pin overrides any software

power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go

into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V).

11

VOUTB

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

12

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on

the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising

edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

13

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

14

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input. The DIN input buffer is powered down after each write cycle.

15

GND

Ground Reference Point for All Circuitry on the Part.

16

SDO

Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the

data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSB, from a straight

line passing through the actual endpoints of the DAC transfer

function. A typical INL versus code plot can be seen in TPC 1.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified DNL of ± 1 LSB maximum ensures

monotonicity. This DAC is guaranteed monotonic by design.

A typical DNL versus code plot can be seen in TPC 4.

Offset Error

This is a measure of the offset error of the DAC and the output

amplifier. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the actual DAC transfer characteristic from the

ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

–6–

REV. A

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