AD5313ARU(RevA) Просмотр технического описания (PDF) - Analog Devices
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производитель
AD5313ARU
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
AD5313ARU Datasheet PDF : 20 Pages
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AD5303/AD5313/AD5323
NOTES
1See Terminology section.
2Temperature range: A, B Version: –40°C to +105°C.
3DC specifications tested with the outputs unloaded.
4Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981).
5Guaranteed by design and characterization, not production tested.
6In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD
and offset plus gain error must be positive.
Specifications subject to change without notice.
AC CHARACTERISTICS1 (VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.)
Parameter2
A, B Version3
Min Typ Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5303
AD5313
AD5323
Slew Rate
Major-Code Transition Glitch Energy
6
8
7
9
8
10
0.7
12
Digital Feedthrough
0.10
Analog Crosstalk
0.01
DAC-to-DAC Crosstalk
0.01
Multiplying Bandwidth
200
Total Harmonic Distortion
–70
NOTES
1Guaranteed by design and characterization, not production tested.
2See Terminology section.
3Temperature range: A, B Version: –40°C to +105°C.
Specifications subject to change without notice.
VREF = VDD = 5 V
µs
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
µs
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
µs
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
V/µs
nV-s 1 LSB Change around Major Carry
(011 . . . 11 to 100 . . . 00)
nV-s
nV-s
nV-s
kHz VREF = 2 V ± 0.1 V p-p, Unbuffered Mode
dB
VREF = 2.5 V ± 0.1 V p-p, Frequency = 10 kHz
TIMING CHARACTERISTICS1, 2, 3
(VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(A, B Version)
Unit
Conditions/Comments
t1
33
t2
13
t3
13
t4
0
t5
5
t6
4.5
t7
0
t8
100
t9
20
t10
20
t11
20
t124, 5
5
t134, 5
20
t145
0
t155
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Rising Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulsewidth
SCLK Falling Edge to LDAC Rising Edge
CLR Pulsewidth
SCLK Falling Edge to SDO Invalid
SCLK Falling Edge to SDO Valid
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3See Figures 1 and 2.
4These are measured with the load circuit of Figure 1.
5Daisy-chain mode only. (See Figure 23.)
Specifications subject to change without notice.
REV. A
–3–
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