HN58C1001T-15 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HN58C1001T-15

1M EEPROM (128-kword × 8-bit) Ready/Busy and RES function

Hitachi -> Renesas Electronics 

HN58C1001 Series

2. Data Protection at VCC On/Off

When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a

trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the

EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.

Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET

signal.

VCC

CPU

RESET

* Unprogrammable

* Unprogrammable

(1) Protection by RES

The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s

RES pin. RES should be kept VSS level during VCC on/off.

The EEPROM brakes off programming operation when RES becomes low, programming operation doesn’t

finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms

after the last data input.

VCC

RES

WE

or CE

Program inhibit

1 µs min 100 µs min

Program inhibit

10 ms min

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