ST93CS47B6013TR Просмотр технического описания (PDF) - STMicroelectronics
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ST93CS47B6013TR Datasheet PDF : 16 Pages
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ST93CS46, ST93CS47
POWER-ON DATA PROTECTION
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit resets all internal programming
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied before
any logic signal.
INSTRUCTIONS
The ST93CS46/47 has eleven instructions, as
shown in Table 6. Each instruction is preceded by
the rising edge of the signal applied on the Chip
Select (S) input (assuming that the Clock C is low),
followed by a ’1’ read on D input during the rising
edge of the clock C. The op-codes of the instruc-
tions are made up of the 2 following bits. Some
instructions use only these first two bits, others use
also the first two bits of the address field to define
the op-code. The address field is six bits long
(A5-A0).
The ST93CS46/47 is fabricated in CMOS technol-
ogy and is therefore able to run from zero Hz (static
input signals) up to the maximum ratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into an output shiftregister. A dummy ’0’ bit is output
first followed by the 16 bit word with the MSB first.
Table 6. Instruction Set
Instruction
Description
W
Pin (1)
READ
Read Data from Memory X
WRITE Write Data to Memory
’1’
PAWRITE Page Write to Memory
’1’
WRALL Write All Memory
’1’
WEN
Write Enable
’1’
WDS
Write Disable
X
PRREAD Protect Register Read
X
PRWRITE Protect Register Write
’1’
PRCLEAR Protect Register Clear
’1’
PREN
Protect Register Enable
’1’
PRDS
Protect Register Disable ’1’
Note: 1. X = don’t care bit.
PRE
Pin
’0’
’0’
’0’
’0’
’0’
’0’
’1’
’1’
’1’
’1’
’1’
Op
Code
10
01
11
00
00
00
10
01
11
00
00
Address (1)
A5-A0
A5-A0
A5-A0
01XXXX
11XXXX
00XXXX
XXXXXX
A5-A0
111111
11XXXX
000000
Data
Q15-Q0
D15-D0
D15-D0
D15-D0
Q8-Q0
Additional
In formation
Write is executed if
the address is not
inside the Protected
area
Write is executed if
all the addresses
are not inside the
Protected area
Write all data if the
Protect Register is
cleared
Data Output =
Protect Register
content + Protect
Flag bit
Data above
specified address
A5-A0 are protected
Protect Flag is also
cleared (cleared
Flag = 1)
OTP bit is set
permanently
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