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P5CD080A4

Secure dual interface and contact PKI smart card controller

NXP Semiconductors. 

NXP Semiconductors

P5Cx012/02x/40/73/80/144 family

Secure dual interface and contact PKI smart card controller

I Versatile EEPROM programming of 1 B to 64 B at a time or, optionally 1 B to 128 B at

a time

I Typical EEPROM page erasing time: 1.7 ms

I Typical EEPROM page programming time: 1.0 ms

N Power-saving Idle mode

N Wake-up from Idle mode by RESET or any activated interrupt

N Power-saving Sleep (power-down) mode or Clockstop mode

N Wake-up from Sleep or Clockstop mode by RESET or external interrupt

I Contact configuration and serial interface according to ISO/IEC 7816: GND, VDD,

CLK, RST_N, IO1

I ISO/IEC 7816 UART supporting standard protocols T = 0 and T = 1 as well as high

speed personalization up to 1 Mbit/s

I External or internally generated configurable CPU clock

I 1 MHz to 10 MHz operating external clock frequency range

N Internal CPU clock up to 30 MHz with synchronous operation

N Internal clocking independent of externally applied frequency

I High speed 16-bit CRC engine according to ITU-T polynomial definition

I Low power Random Number Generator (RNG) in hardware, AIS-31 compliant

I 1.62 V to 5.5 V extended operating voltage range for class C, B and A

I Optional extended Class B operation mode (targeted for battery supplied applications)

I −25 °C to +85 °C ambient temperature

I Broad spectrum of delivery types:

N Wafers

N Modules

2.2 Product specific family features

I P5CC021, P5CC040, P5CC073, P5CC080 and P5CC144

N ISO/IEC 7816 contact interface

N Two additional IO ports IO2 and IO3 for full-duplex serial data communication

I P5CD012, P5CD020, P5CD040, P5CD080 and P5CD144

N CIU fully compatible with ISO/IEC 14443 A:

- Fully supports the T = CL protocol according ISO/IEC 14443-4

- Data transfer rates supported: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s

N MIFARE contactless interface according ISO/IEC 14443-2:

- 13.56 MHz operating frequency

- Reliable communication due to 100 % ASK

- High speed efficient frame support

- True anticollision

N MIFARE reader infrastructure compatibility

N Optional MIFARE 1 KB and MIFARE 4 KB emulation

N Two additional IO ports IO2 and IO3 for full-duplex serial data communication

I P5CN080 and P5CN144

N S2C interface

N One additional IO port IO2 for full-duplex serial data communication

P5CX012_02X_40_73_80_144_FAM_SDS_3

Objective short data sheet

Rev. 03 — 24 January 2008

© NXP B.V. 2008. All rights reserved.

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