LH7A404 Просмотр технического описания (PDF) - NXP Semiconductors.
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LH7A404 Datasheet PDF : 75 Pages
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LH7A404
NXP Semiconductors
32-Bit System-on-Chip
LFBGA
SIGNAL
N17 A2/SA0
M19 A3/SA1
M20 A4/SA2
L20 A5/SA3
M17 A6/SA4
K18 A7/SA5
K20 A8/SA6
K19 A9/SA7
J20 A10/SA8
H20 A11/SA9
J17 A12/SA10
H18 A13/SA11
F20 A14/SA12
G18 A15/SA13
H16 A16/SB0
F18 A17/SB1
G17 A18
F17 A19
D19 A20
E17 A21
C19 A22
D17 A23
B19 A24
A16 A25
D15 A26
B14 A27
V18 nCS0
R19 nCS1
R18 nCS2
P19 nCS3
R20 nCS6
R17 nCS7
C12 nOE
D12 nWE
P18 nWAIT
C17 nSCS0
A19 nSCS1
D16 nSCS2
E16 nSCS3
B16 nSWE
A14 SCKE0
B13 SCKE1_2
Table 2. LH7A404 Functional Pin List (Cont’d)
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
I/O
NOTES
Asynchronous Address Bus and
Synchronous Address Bus
LOW
LOW
12 mA O
• Asynchronous Address Bus
• Synchronous Device Bank Address 0
• Asynchronous Address Bus
• Synchronous Device Bank Address 1
Asynchronous Address Bus
Asynchronous Address Bus
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
12 mA O
12 mA O
12 mA O
12 mA O 4
Asynchronous Address Bus
LOW
LOW
12 mA O
Asynchronous Memory Chip Select 0
Asynchronous Memory Chip Select 1
Asynchronous Memory Chip Select 2
Asynchronous Memory Chip Select 3
Asynchronous Memory Chip Select 6
Asynchronous Memory Chip Select 7
Asynchronous Memory Output Enable
Asynchronous Memory Write Enable
Asynchronous Memory Wait; pull HIGH if unused
Synchronous Memory Chip Select 0
Synchronous Memory Chip Select 1
Synchronous Memory Chip Select 2
Synchronous Memory Chip Select 3
Synchronous Memory Write Enable
Clock Enable 0 for Synchronous Memory
Clock Enable 1 OR 2 for Synchronous Memory
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Input
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
12 mA O
HIGH
12 mA O
HIGH
12 mA O
HIGH
12 mA O
No Change 12 mA O
No Change 12 mA O
HIGH
12 mA O 4
HIGH
12 mA O 4
No Change
I
5
HIGH
12 mA I/O
HIGH
12 mA I/O
HIGH
12 mA I/O
HIGH
12 mA I/O
HIGH
12 mA O
No Change 12 mA O
No Change 12 mA O
6
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