AD7609 Просмотр технического описания (PDF) - Analog Devices
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AD7609 Datasheet PDF : 36 Pages
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Data Sheet
AD7609
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/ internal reference, TA = TMIN to TMAX,
unless otherwise noted.1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
tCONV
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
t52
t6
t7
PARALLEL READ OPERATION
t8
t9
t10
t11
t12
Limit at TMIN, TMAX
Min Typ Max
5
5
10.1
11.5
3.45 4 4.15
7.87
9.1
16.05
18.8
33
39
66
78
133
158
257
315
100
30
13
50
20
20
45
25
25
0
0.5
25
25
0
0
19
24
30
37
15
22
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
1/throughput rate
Parallel mode, reading during; or after conversion VDRIVE = 2.7 V to 5.25 V; or
serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA
and DOUTB lines
Parallel mode reading after conversion VDRIVE = 2.3 V
Serial mode reading after conversion; VDRIVE = 2.7 V, DOUTA and DOUTB lines
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
Oversampling off
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
STBY rising edge to CONVST x rising edge; power-up time from standby mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CS rising edge and BUSY falling edge
Minimum delay between RESET low to CONVST x high
CS to RD setup time
CS to RD hold time
RD low pulse width
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
Rev. B | Page 7 of 36
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