Enhanced PCI Bus Multimedia Controller
14.2 Video Bus Timing
Table 17: Video Bus Timing
Symbol
Parameter
Min
tV2P
VCLKx2 period
31
tV2T
VCLKx2 rise/fall transition
tVT
VCLK rise/fall transition
tVIS
Video bus input setup
11
tVIH
Video bus input hold
0
tVCLKH
VCLK hold
-2
Max
Unit
45
ns 40% to 60% duty cycle
5
ns
5
ns
ns
ns
ns
VCLKx2
VCLK
INPUTS
tV2P
tVIS
tV2T
tVCLKH
tVIS
tVIH
tV2T
Figure 11. Video Bus Timing
Table 18: Video Bus Outputs
Symbol
tVBO
tVBH
tVPO
tVPH
Parameter
Video bus output delay
Video bus output hold (all signals except PXEN)
PXEN output delay
PXEN output hold
Min
Max
Unit
1
16
ns Typical output Load 50pf
1
ns
17
ns
2
ns
VCLK
VCLKx2
VIDEO OUTPUT
PXEN
tVPO
tVBO
tVPH
tVBH
Figure 12. Video Bus Timing – Control and Data Output Signals
38